Static Random Access Memory (SRAM) 6-transistor memory cells typically consist of 4 n-channel transistors and 2 p-channel transistors. FIG. 1 shows an example of such a cell 10. P-channel transistor P1 and n-channel transistor N1 form one inverter. and P2 and N3 for another inverter. The connections between the two inverters cause the output of each inverter to drive the input of the other, forming a cross-coupled latch 12. The remaining two n-channel transistors, N2 and N4, provide access to the input/output of the two inverters.
In the absence of the two access n-channel transistors N2 and N4, the cross-coupled latch 12 retains the state of any data written into the memory cell, with one inverter outputting a ‘0’ and the other a ‘1.’ If one or both of the p-channel transistors are weak or missing, the cell will fail to retain the data state for extended periods of time due to the inability of a weak or missing p-channel transistor to maintain the high state. Even with weak or missing p-channel transistors, the cell will retain the data dynamically for extended periods of time, ranging from many milliseconds to seconds.
Normal memory testing will identify the presence or absence of the n-channel transistors. Testing for the presence or absence of the p-channel transistors presents some problems. The test to identify the cells with missing or weak p-channel transistors typically writes a pattern, waits an extended period of time, and verifies the data state of the cell, then writes data that is the complement of the first pattern, again waits an extended period of time, and verifies the data state of the cell. Using complement data allows both data states to be tested. These tests may take many seconds to accomplish and may still result in suspect data, as the waiting period may not have been long enough to detect a cell failure as there is no way to reliably predict how long a faulty cell will retain data. No reliable, quick test for p-channel transistors in SRAM memory cells currently exists.